1. Field of the Invention
This invention relates generally to impedance matching of high-frequency, high-power semiconductor devices and, more particularly, to impedance matching by use of a dielectric element in combination with high density interconnect (HDI) technology.
2. Description of Related Art
Electronic devices have inherent impedance characteristics associated with both inputs and outputs. These impedances dictate the transmission characteristics of each device. Impedance mismatches between interconnected devices and between sequential devices and transmission lines cause losses of power, gain and efficiency. Impedance is frequency dependent; the higher the operating frequency, the more noticeable mismatching effects become. In very high frequency devices, including monolithic microwave integrated circuits, impedance mismatches can render a circuit unusable.
By impedance matching we mean the practice of designing circuits to reduce impedance mismatches, thereby improving gain and efficiency of the circuit. Impedance matching techniques employ capacitive and inductive means to compensate for impedance differences.
It is known in the art to fabricate circuit modules having a substrate on which is located electronic devices (including integrated circuits chips and supporting components), microstrip circuits, DC supply lines, and logic lines. Electrical interconnections are then made using wire bonds or tab interconnections.
It is known in the art to match the impedances of the various devices of such a circuit by employing patterned metal matching strips over a dielectric material, where the dielectric material is situated above a ground plane. The patterned metal matching strips are usually formed using thin and thick film fabrication techniques. The resultant impedance matching characteristics are determined by the shape, width, thickness, and conductivity of both the patterned metal matching strips and the ground plane as well as by the shape, width, thickness and capacitive characteristics of the interposed dielectric material. These patterned metal strips can be used to connect one chip to another chip located on the same substrate or they can be used to connect a chip to a transmission line for connection to an external device.
Thin and thick film fabrication techniques and wire bond and tab interconnection techniques, however, have a number of disadvantages. Thin and thick film methods of fabricating circuitry on ceramic substrates have tolerance limitations which prevent such structures from being produced with microwave characteristics which are repeatable within close tolerances. As a result, there are frequently substrate-to-substrate variations in the impedance characteristics of such nominally identical substrates. In addition, active microwave components themselves have fabrication tolerances which result in variations in operating characteristics from device to device. Impedance discontinuities also vary with the actual placement of the chips on the surface, or in cavities, of the ceramic substrate. This is because slight changes in the positioning of a device alters the distance between the device and the substrate and result in variable interconnect bond lengths, thereby introducing additional impedance mismatches. Impedance mismatches also vary according to the materials employed in fabrication of the components, the substrates and the wire bond and tab interconnections. The cumulative effect of all of these differences is a wide range of system operating characteristics. Although matching patterns may be modified during manufacturing to compensate for these variations, such a practice becomes increasingly difficult as the number of chips on a substrate is increased.
Another drawback of these types of systems is the fact that many active microwave components cannot be accurately tested over their full expected operating frequency and power ranges in a non-destructive manner. Many components which pass preassembly testing, therefore, do not, in reality, meet specifications. Since few of these structures are designed to permit reworking or replacement of faulty components, neither the components nor their connections can be removed in a non-destructive manner. Manufacturing high frequency systems from such components is, therefore, a relatively low yield process in which many of the resulting systems do not meet specifications. It is desirable to increase yield by employing a deformable type of component interconnect, such as the HDI system.
A high density interconnect (HDI) system offers many advantages in the compact assembly of digital systems employing semiconductor devices and other electronic systems. For example, an electronic system incorporating between 30 and 50 chips can be fully assembled and interconnected on a single substrate 2 inches long by 2 inches wide by 0.050 inch thick. More importantly, the system can be disassembled for repair or replacement of a faulty component or interconnection. The system can then reassembled without significant risk to the system's good components. This is especially important where particularly expensive chips are incorporated into a system.
Briefly, in this high density interconnect system, a ceramic substrate, such as alumina, which may be 25-100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square but may be larger or smaller. Once the position of the various chips has been specified, individual cavities are formed having appropriate depths at the intended locations of the chips. Conventional laser or ultrasonic milling may be used to form the cavities in which the various chips and other components will be positioned. Where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. Typically the cavity or cavities will be of substantially uniform depth. Where a particularly thick or a particularly thin component will be placed, however, the cavity bottom must be made respectively deeper or shallower to ensure that the upper surface of that component will lie substantially in the same plane as the upper surface of the rest of the components and in the same plane formed by the upper surface of the substrate surrounding the cavity. The bottom of each cavity is provided with a conductive epoxy or eutectic solder layer used to attach the various components which are placed in their desired locations within each cavity.
Thereafter, a film (which may be "KAPTON".RTM. polyimide, available from E. I. du Pont de Nemours Company, Wilmington, Del.), of a thickness of approximately 0.0005-0.003 inches (approx. 12.5-75 microns), is pre-treated by reactive ion etching (RIE) to promote adhesion. The substrate and chips must then be coated with "ULTEM 1000".RTM. polyetherimide resin or another thermoplastic adhesive to adhere the "KAPTON".RTM. resin film when it is laminated across the tops of the chips and across any other components and the exposed portion of the substrate.
Next, via holes are provided through the "KAPTON".RTM. resin film and "ULTEM".RTM. resin layers at locations in alignment with the terminals on the electronic components to which it is desired to make contact.
A metallization layer, comprising a first sub-layer of titanium (approximately 1000.ANG.) and a second sub-layer of copper (approximately 2000.ANG.), is sputter deposited over the "KAPTON".RTM. resin layer, extending into the via holes to make electrical contact to the terminals disposed thereunder. The sputtered copper provides a seed layer for copper electroplating (3 to 4 microns thick). A final sub-layer of titanium (100.ANG.) is sputter deposited to complete the Ti/Cu/Ti multi-layer metallization. This metallization layer is then patterned to form individual conductors using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any mispositioning of the individual electronic components is compensated for by adaptive laser lithography.
This high density interconnect structure provides many advantages. Included among these are the lightest weight and smallest volume packaging of such an electronic system presently available. A further advantage of this high density interconnect structure is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require individual prepackaging of each semiconductor device. Prior art processes also require multi-layer circuit boards to interconnect the individual semiconductor devices. Multi-layer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only element which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, except where cavities of various depths are required. Such cavities may be formed in an already fired ceramic substrate by conventional or laser milling. This process is straight forward and fairly rapid. Once a desired configuration of the substrate is established, cavities can be prepared in a substrate and the semiconductor chips can be mounted in as little as one day.
High density interconnect structures have also been developed for microwave systems. Developments include air gaps over sensitive microwave structures, test terminals and impedance matching circuits.
High density interconnect structures, methods of fabrication it and tools for fabrication disclosed in U.S. Pat. No. 4,783,695, "Multichip Integrated Circuit Packaging Configuration and Method," by Eichelberger, et al.; U.S. Pat. No. 5,206,712, "Building Block Approach to Microwave Modules," by Kornrumpf, et al.; and U.S. Pat. No. 5,355,102, "HDI Impedance Matched Microwave Circuit Assembly," by Kornrumpf, et al. These patents, including the references cited therein, are hereby incorporated in their entireties by reference.
As disclosed and claimed in the last-mentioned patent, located in a substrate is a chip having an electrode whose impedance is to be matched. A first dielectric layer is formed over the chip and the surrounding substrate. A via hole is formed in the dielectric layer to expose the electrode. A first patterned metal layer is formed over the first dielectric layer, making contact with the microwave terminals on the chips through the via holes. A second dielectric layer is formed over the patterned metal layer. A second patterned metal layer is then formed over the second dielectric layer. The second patterned metal layer is grounded. An impedance matching capacitor is formed by the first patterned metal layer, the grounded second patterned metal layer, and the second dielectric layer located between the two metal layers. The matching characteristics of the capacitor vary according to the shape and surface area of the patterned metal layers and by the thickness, shape and dielectric properties of the second dielectric layer.
The impedance matched circuit taught in the above mentioned patent, while useful for low to moderate power applications, may not, however, be suitable for all high power applications. This is because impedance matching of some high power circuits requires relatively high capacitive values with relatively small areas. High capacitive values are achieved by employing dielectric materials having high dielectric constants, by increasing the surface area of the patterned metal conductors, by decreasing the thickness of the dielectric material, or through some combination of the above. However, due to the small variety of materials suitable for use as a dielectric layer and the relatively small surface areas available, high capacitive values are achieved primarily by stretching the dielectric layer extremely thin. This, however, may cause tears in the dielectric layer or leave the dielectric layer so thin that electrical arcing between the matching circuit and the ground plane may occur. Consequently, it is desired to provide an improved high density interconnect structure for impedance matching of high-power, high-frequency integrated circuits.